Fabrication of single-molecule SETs

The figure above contains a selection of images of our SET devices. In A is shown a 3-D view of the chip design containing five sets of six nanowires. A photograph of the entire chip is shown in B. A total of 30 nanowires is obtained on each chip. In every run we fabricate 16 chips, which makes a total of 480 nanowires per run. (Having a very large number of nanowires is of crucial importance due to the low yield of the technique employed to generate molecular SETs.) The device fabrication procedure is the following (see A). A thin (20 nm) Au layer patterned according to the lead geometry is deposited on a Si/SiO₂ wafer (1 m thick SiO₂ top layer to prevent leaks). A thick (200 nm) Au layer (yellow) is then deposited on top to decrease the overall resistance of the leads and help in wire-bonding the contacts to the chip holder. Note that the ends of the leads (orange) are left thin. A narrow Al gate electrode (grey), 20 nm thick, is deposited while maintaining the sample cold (77 K) during evaporation. This helps to obtain a smooth flat Al surface. The Al is left at atmospheric conditions overnight to obtain a thin (2-3 nm) Al₂O₃ layer. The gate is connected to two electrode leads (upper-left and lower-right regions in A). All steps up to this point are done exclusively with optical lithography. The final step in the process is the patterning of thin (18 nm) gold nanowires by means of state-of-the-art EBL technology available to the PI at UCF. C shows an AFM image of one of the nanowires deposited on top of the Al-gate. A zoom on the nanowire center (D) obtained by SEM shows a nanowire approximately 200 nm long and 90 nm wide. All components of the circuit and steps in the process were tested repeatedly until an optimal design was obtained

Figure above shows the electromigration-induced breaking (T = 4 K) of several nanowires (A). The current across the nanowires increases linearly with the voltage until the rupture point, when a gap is created and, consequently, the current abruptly drops to zero at a given breaking voltage, V_break. A resistor (20, 110, or 205 Ohms) in series with the nanowire (30 Ohms) is used to tune the breaking voltage. B shows the breaking voltage dependence of the tunnel resistance of the gap measured at low bias voltages (the zero-bias resistance, ZBR) of several wires after breaking. The increase of the resistance with the breaking voltage is associated to the gap formation during the electromigration-induced breaking of the nanowire, which is mainly determined by the current density. It is well known that for a given current density the higher the voltage the wider the gap. The tunnel resistance varies between 10 k and 100 G for most wires. According to previous studies, this huge variation corresponds to just about a 1 nm variation in gap size. This means that our gap sizes are in the 1-3 nm size range. The current density necessary to break a Au nanowire is estimated to be j_b = 5x10¹² A/m² and the breaking current I_break necessary to achieve this characteristic current density depends on the cross section area of the nanowire. Therefore, the breaking voltage is determined by the total resistance of the circuit, namely V_break = R_TI_break, where R_T = R_nw+R_series. Consequently, a series resistor can be used to control the breaking voltage, and therefore engineer the size of the gap. The histogram in C shows the distribution of breaking currents centered at around 8.5 mA. Considering a cross section area of 90 nm (width) 18 nm (thickness) for our nanowires, we obtain j_b = 5.3x10¹² A/m², which is in excellent agreement with the value given in literature. If we associate the change in breaking currents (I_break ~ 2 mA) to variations of the nanowire thickness, this indicates a 3.4 nm thickness variation along the four-inch long Si wafer used to fabricate the chips. This variation is likely due to the dispersion of the Au evaporation beam along the wafer (solid angle). In D we show four different types of I-V curves found after the formation of the gap and E shows the statistics of each of the curves together with the wires showing no current (NC) after breaking (most likely due to an extra-large gap formation). The I-V curves of broken wires can then be grouped according to the following classification: a) CB, curves with current suppression for low bias voltages consistent with the Coulomb blockade effect; b) STP, curves showing abrupt changes of current (steps) consistent with quantization of the conductance; c) ZBE, zero bias enhancement of the conductance consistent with low-temperature Kondo effect; and d) SMH, smooth asymmetric curves not crossing I=V=0.